1. Field of the Invention
The present invention relates to a horizontal synchronizing signal separation circuit, and more particularly to a horizontal synchronizing signal separation circuit for extracting the timing of a horizontal synchronizing signal from a composite synchronizing signal which includes a horizontal synchronizing signal and a vertical synchronizing signal. Hereinafter, the term "synchronizing signal" is abbreviated as "sync signal".
2. Description of the Background Art
In a television system such as the NTSC (National Television System Committee) system or the PAL (Phase Alternation Line) system, only a composite sync signal in which a vertical sync signal and a horizontal sync signal are combined is supplied as a sync signal to a television apparatus.
In a matrix type liquid crystal display (LCD) apparatus widely used in recent years, a clock signal for sampling image signals in the LCD apparatus is generated. Since this clock signal must be precisely synchronous with the horizontal sync signal when the display is performed based on the image information in the above-mentioned television system, the clock signal is generated using a PLL (Phase-Locked Loop) circuit 100 as shown in FIG. 9. The PLL circuit 100 has a loop which comprises a voltage-controlled oscillator (VCO) 101, a frequency divider 102, a phase comparator 103 and a low-pass filter (LPF) 104. It is desirable to supply the horizontal sync signal as the sync signal Sync which is the input signal of the PLL circuit 100. In the prior art, however, the composite sync signal is supplied as it is.
FIGS. 10A to 10C show composite sync signals used in the NTSC system. FIG. 10A shows a composite sync signal in a transition period from an even field to an odd field. FIG. 10B shows a portion of a composite sync signal in one field. In FIG. 10C, a composite sync signal in a transition period from an odd field to an even field is illustrated. As shown in FIGS. 10A and 10C, in addition to the horizontal sync signal 21, a vertical sync signal and an equalizing pulse 22 exist in the composite sync signal in the transition period from one field to the next field. The equalizing pulse 22 is inserted to equalize the waveforms of the composite sync signal in the portion of the vertical sync signal and in the peripheral portion thereof, during the transition period from the even field to the odd field and during the transition period from the odd field to the even field. In the peripheral portion of the vertical sync signal, the width of the horizontal sync signal 21 and that of the equalizing pulse 22 are half as compared with that of the normal horizontal sync signal 21.
In the prior art, since such a composite sync signal is input to the PLL circuit 100 (FIG. 9) as it is, the phase relationship in the PLL circuit 100 is disturbed due to the presence of the vertical sync signal and equalizing pulse in the composite sync signal shown in FIGS. 10A and 10C. This disturbance causes the oscillation frequency of the VCO 101 to fluctuate. If this fluctuation in the oscillation frequency of the VCO 101 is not absorbed even when entering a display period during which image information for the display area is supplied to the LCD apparatus, a problem arises in that the resulting image is distorted.
In order to avoid the image distortion from occurring, it is necessary to absorb the fluctuation in the oscillation frequency of the VCO 101 during a period prior to the above display period (i.e., a vertical retrace line interval). This is a major hindrance in the simplification of the design of the PLL circuit for a matrix type display apparatus such as an LCD apparatus.
Further, in some prerecorded video tapes which are commercially available, an AGC (Auto Gain Control) signal for the luminance signal is purposely inserted in the composite video signal in order to destabilize the playback of video tapes produced by copying the prerecorded video tapes. In the playback of these video tapes, the AGC signal cannot be completely removed by a low-pass filter in the extraction of the composite sync signal from the composite video signal, and therefore, a pulse (which may be a spurious sync signal such as that shown in FIG. 11) in mixed in immediately after the vertical sync signal in the extracted composite sync signal. When a composite sync signal in which the spurious sync signal exists immediately before the display period as shown in FIG. 11 is input to the PLL circuit 100, it is practically impossible to stabilize the PLL circuit 100 which is disturbed by the spurious sync signal, before the display period. In order to solve this problem in the prior art, such measures as narrowing the area in which the image is actually displayed on the display screen are employed, but it was difficult to completely hide the image distortion appearing in the upper portion of the display screen, and satisfactory display can not be obtained in many cases.